1. Field of the Invention
This invention relates to charge coupled devices (CCD) and particularly to CCD readout registers which have multiple output structures for high data rate focal plane applications.
2. Description of Related Art
Two dimensional imaging arrays generally take a snap shot of an image where the whole photoactive array of pixels integrates photogenerated charge for a period of time. At the end of the integration time, the information is transferred from the sensor to an external circuit element using a parallel to serial transfer scheme. Each line of pixel data is transferred into a horizontal CCD shift register. The line of data is then transferred serially to an output device at the end of the register.
Generally the data rate at which signal charge can be transferred is limited by the bandwidth of the output device.
In applications where the data rate must be in excess of the amplifier bandwidth, the horizontal CCD shift register must be partitioned into subregisters. Each subregister or register segment will then transfer signal charge to its own separate output device which operates at the bandwidth limit of the output device. The data is then multiplexed off-chip to reconstruct the image at the higher data rate which is the amplifier bandwidth multiplied by the number of output devices or taps. This register architecture is known as a multi-tapped horizontal readout register.
Tapped register designs require placement of an output device within the horizontal pitch of the register. For high density CCD sensor designs where the pitch is small in view of the minimum dimensions permitted by the design rules for the state of the processing technology used to make the CCD, it is difficult to position an output device within the register pitch such that the output device will have high performance (high conversion efficiency and low noise) while not sacrificing the performance of the horizontal register.
This invention solves the problem of placing a high performance output device within one element of a high density horizontal CCD shift register such that the adjacent shift register elements are not altered in performance. This invention allows for a partial reduction in the area of the first element of a register segment adjacent an output tap without reducing the charge handling capacity of that element.
The invention may be generally applied to any CCD layout which requires that CCD register elements have unequal physical dimensions but which require the same charge handling capacity. In brief, this invention allows for the equilibration of maximum charge handling capacity for CCD well areas of different size. For example, a 10 micron by 10 micron register element can be made to have the same charge handling capacity as a 10 micron by 15 micron register element.
In previous work, this charge handling equilibration would have been achieved making use of stepped oxides under the polysilicon CCD gate electrodes thereby increasing or decreasing the capacitance of the register element. The stepped oxide technique is not very satisfactory since it is difficult to control the process and the electrical parameters of the register element. The stepped oxide technique is not cost effective. This invention improves the state of the art in that it allows for equilibration of charge handling capacity with a simple implant step. This invention uses the concept of a special implant to create a buried channel CCD notch or trench in a register element (see U.S. Pat. No. 4,667,213 granted May 19, 1987 to Kosonocky). The trench is used to increase the charge storage per unit area of a small pitch CCD shift register and to improve the charge transfer efficiency of the register for small signals in cooled devices.